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| FLASH Austin Semiconductor, Inc. 128K x 8 FLASH UNIFORM SECTOR 5.0V FLASH MEMORY AVAILABLE AS MILITARY SPECIFICATIONS * MIL-STD-883 * SMD 5962-96690 NC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS AS29F010 PIN ASSIGNMENT (Top View) 32-PIN Ceramic DIP (CW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC WE\ NC A14 A13 A8 A9 A11 OE\ A10 CE\ DQ7 DQ6 DQ5 DQ4 DQ3 FEATURES * Single 5.0V 10% power supply operation * Low power consumption: ! 12 mA typical active read current ! 30 mA typical program/erase current ! <1 A typical standby current * Flexible sector architecture ! Eight 16Kbyte sectors ! Any combination of sectors can be erased ! Full chip erase * Sector protection ! Hardware-based feature that disables/reenables program and erase operations in any combination of sectors ! Sector protection/unprotection can be implemented using standard PROM programming equipment * Embedded Algorithms ! Embedded Erase algorithm automatically pre-programs and erases the chip or any combination of designated sectors ! Embedded Program algorithm automatically programs and verifies data at specified address * Erase Suspend/Resume ! Supports reading data from a sector not being erased * Minimum 1 million erase cycles guaranteed per sector * Compatible with JEDEC standards ! Pinout and software compatible with single-powersupply FLASH ! Superior inadvertent write protection * Data\ Polling and Toggle Bits ! Provides a software method of detecting program or erase cycle completion OPTIONS * Timing 50ns* 60ns 70ns 90ns 120ns 150ns * Package Ceramic DIP (600 mil) MARKING -5 -6 -7 -9 -12 -15 CW For more products and information please visit our web site at www.austinsemiconductor.com * Temperature Industrial Temperature (-40C to +85C) IT Military Temperature (-55C to +125C) XT 883C Processing (-55C to +125C) 883C QML Processing (-55C to +125C) Q NOTES: only. *50ns (-5) option available with IT, XT, and 883C options AS29F010 Rev. 0.3 10/02 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 1 FLASH Austin Semiconductor, Inc. GENERAL DESCRIPTION The AS29F010 is a 1Mbit, 5.0 Volt-only FLASH memory organized as 131,072 bytes. The AS29F010 is offered in a 32-pin CDIP package. The byte-wide data appears on DQ0-DQ7. The device is designed to be programmed in-system with the standard system 5.0 Volt VCC supply. A 12.0 volt VPP is not required for program or erase operations. The device can also be programmed or erased in standard EPROM programmers. This device is manufactured using 0.32 m process technology. It is available with access times of 50, 60, 70, 90, 120, and 150ns, allowing high-speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE\), write enable (WE\), and output enable (OE\) controls. The device requires only a single 5.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply FLASH standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other FLASH or EPROM devices. Device programming occurs by executing the program command sequence. This invokes the Embedded Program algorithm -- an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Device erasure occurs by executing the erase command sequence. This invokes the Embedded Erase algorithm -- an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by reading the DQ7 (Data\Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is erased when shipped from the factory. The hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory, and is implemented using standard EPROM programmers. The system can place the device into the standby mode. Power consumption is greatly reduced in this mode. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The bytes are programmed one byte at a time using the EPROM programming mechanism of hot electron injection. AS29F010 PIN CONFIGURATION PIN A0 - A16 DQ0 - DQ7 CE\ OE\ WE\ VCC VSS NC DESCRIPTION 17 Addresses 8 Data Inputs/Outputs Chip Enable Output Enable Write Enable +5 Vold Single Power Supply Device Ground No Connect LOGIC SYMBOL AS29F010 Rev. 0.3 10/02 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 2 FLASH Austin Semiconductor, Inc. FUNCTIONAL BLOCK DIAGRAM AS29F010 AS29F010 Rev. 0.3 10/02 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 3 FLASH Austin Semiconductor, Inc. DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The appropriate device bus operations table lists the inputs and control levels required, and the resulting output. The following subsections describe each of these operations in further detail. AS29F010 Writing Commands/Command Sequences To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE\ and CE\ to VIL, and OE\ to VIH. An erase operation can erase one sector, multiple sectors, or the entire device. The Sector Address Tables indicate the address space that each sector occupies. A "sector address" consists of the address bits required to uniquely select a sector. See the "Command Definitions" section for details on erasing a sector or the entire chip. After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7 - DQ0. Standard read cycle timings apply in this mode. Refer to the "Autoselect Mode" and "Autoselect Command Sequence" sections for more information. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The "AC Characteristics" section contains timing specification tables and timing diagrams for write operations. Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE\ and OE\ pins to VIL. CE\ is the power control and selects the device. OE\ is the output control and gates array data to the output pins. WE\ should remain at VIH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See "Reading Array Data" for more information. Refer to the AC Read Operations table for timing specifications and to the Read Operations Timings diagram for the timing waveforms. ICC1 in the DC Characteristics table represents the active current specification for reading array data. Program and Erase Operation Status During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7 - DQ0. Standard read cycle timings and ICC read specifications apply. Refer to "Write Operation Status" for more information, and to each AC Characteristics section in the appropriate data sheet for timing diagrams. TABLE 1: DEVICE BUS OPERATIONS OPERATION Read Write Standby Output Disable Hardware Reset CE\ L L VCC 0.5V L X OE\ L H X H X WE\ H L X H X Addresses1 DQ0 - DQ7 AIN AIN X X X DOUT DIN High-Z High-Z High-Z NOTES: 1. Addresses are A16:A0. 2. The sector protect and sector unprotect functions must be implemented via programming equipment. See the "Sector Protection/ Unprotection" section. AS29F010 Rev. 0.3 10/02 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 4 FLASH Austin Semiconductor, Inc. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE\ input. The device enters the CMOS standby mode when the CE\ pin is held at VCC 0.5V. (Note that this is a more restricted voltage range than VIH.) The device enters the TTL standby more when CE\ is held at VIH. The device requires the standard access time (tCE) before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. ICC3 in the DC Characteristics table represents the standby current specification. AS29F010 address bits that are don't care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7 - DQ0 To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in the Command Definitions table. This method does not require VID. See "Command Definitions" for details on using the autoselect mode. Sector Protection/Unprotection The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. Sector protection/unprotection must be implemented using programming equipment. The procedure requires a high voltage (VID) on address pin A9 and the control pins. The device is shipped with all sectors unprotected. It is possible to determine whether a sector is protected or unprotected. See "Autoselect Mode" for details. Output Disable Mode When the OE\ input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state. Autoselect Mode The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7 - DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires VID on address pin A9. Address pins A6, A1, and A0 must be as shown in the Autoselect Codes (High Voltage Method) table. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits. Refer to the corresponding Sector Address Tables. The Command Definitions table shows the remaining Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to the Command Definitions table). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise. Low VCC Write Inhibit When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/ TABLE 2: SECTOR ADDRESSES TABLE SECTOR SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 A16 0 0 0 0 1 1 1 1 A15 0 0 1 1 0 0 1 1 A14 0 1 0 1 0 1 0 1 ADDRESS RANGE 00000h - 03FFFh 04000h - 07FFFh 08000h - 0BFFFh 0C000h - 0FFFFh 10000h - 13FFFh 14000h - 17FFFh 18000h - 1BFFFh 1C000h - 1FFFFh NOTE: All sectors are 16 Kbytes in size. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. AS29F010 Rev. 0.3 10/02 5 FLASH Austin Semiconductor, Inc. erase circuits are disabled, and the device resets. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO. Write Pulse "Glitch" Protection Noise pulses of less than 5ns (typical) on OE\, CE\, or WE\ do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE\ = VIL, CE\ = VIH or WE\ = VIH. To initiate a write cycle, CE\ and WE\ must be a logical zero while OE\ is a logical one. Power-Up Write Inhibit If WE\ = CE\ = VIL and OE\ = VIH during power up, the device does not accept commands on the rising edge of WE\. The internal state machine is automatically reset to reading array data on power-up. AS29F010 Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect mode. See the "Reset Command" section, next. See also "Requirements for Reading Array Data" in the "Device Bus Operations" section for more information. The Read Operations table provides the read parameters, and the Read Operation Timings diagram shows the timing diagram. Reset Command Writing the reset command to the device resets the device to reading array data. Address bits are don't care for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data. If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data. COMMAND DEFINITIONS Writing specific address and data commands or sequences into the command register initiates device operations. The Command Definitions table defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. All addresses are latched on the falling edge of WE\ or CE\, whichever happens first. Refer to the appropriate timing diagrams in the "AC Characteristics" section. TABLE 3: Autoselect Codes (High Voltage Method) DESCRIPTION Manufacturer ID Device ID Sector Protection Verification CE\ L L OE\ L L WE\ H H A16 to A13 to A9 A14 A10 X X X X VID VID A8 to A7 X X A6 L L A5 to A2 X X A1 L L A0 L H DQ7 to DQ0 01h 20h 01h (protected) L L H SA X VID X L X H L 00h (unprotected) NOTE: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don't Care Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. AS29F010 Rev. 0.3 10/02 6 FLASH Austin Semiconductor, Inc. Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. The Command Definitions table shows the address and data requirements. This method is an alternative to that shown in the Autoselect Codes (High Voltage Method) table, which is intended for PROM programmers and requires VID on address bit A9. The auto select command sequence is initiated by writing two unlock cycles, followed by the autoselect command. The device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. A read cycle at address XX00h or retrieves the manufacturer code. A read cycle at address XX01h returns the device code. A read cycle containing a sector address (SA) and the address 02h in returns 01h if that sector is protected, or 00h if it is unprotected. Refer to the Sector Address tables for valid sector addresses. The system must write the reset command to exit the autoselect mode and return to reading array data. AS29F010 command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. The Command Definitions table shows the address and data requirements for the chip erase command sequence. Any commands written to the chip during the Embedded Erase algorithm are ignored. The system can determine the status of the erase operation by using DQ7 or DQ6. See "Write Operation Status" for information on these status bits. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. Figure 2 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in "AC Characteristics" for parameters, and the Chip /Sector Erase Operation Timings for timing waveforms. Byte Program Command Sequence Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verify the programmed cell margin. The Command Definitions take shows the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using DQ7 or DQ6. See "Write Operation Status" for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a "0" back to a "1". Attempting to do so may halt the operation and set DQ5 to "1", or cause the Data\ Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still "0". Only erase operations can convert a "0" to a "1". FIGURE 1: PROGRAM OPERATION Chip Erase Command Sequence Chip erase is a six-bus-cycle operation. The chip erase AS29F010 Rev. 0.3 10/02 NOTE: 7 See the appropriate Command Definitions table for program command sequence. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. FLASH Austin Semiconductor, Inc. Sector Erase Command Sequence Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the addresss of the sector to be erased, and the sector erase command. The Command Definitions table shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram the memory prior to erase. The Embedded Erase algorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of 50s begins. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50s, otherwise the last address and command might not be accepted, and erasure may begin. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. If the time between additional sector erase commands can be assumed to be less than 50s, the system need not monitor DQ3. Any command during the time-out period resets the device to reading array data. The system must rewrite the command sequence and any additional sector addresses and commands. The system can monitor DQ3 to determine if the sector erase timer has timed out. (See the "DQ3: Sector Erase Timer" section.) The time-out begins from the rising edge of the final WE\ pulse in the command sequence. Once the sector erase operation has begun, all other commands are ignored. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7 or DQ6. Refer to "Write Operation Status" for information on these status bits. Figure 2 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in the "AC Characteristics" section for parameters, and to the Sector Erase Operations Timing diagram for timing waveforms. AS29F010 command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. Writing the Erase Suspect command during the Sector Erase time-out immediately terminates the time-out period and suspends the erase operation. Addresses are "don't cares" when writing the Erase Suspect command. When the Erase Suspect command is written during a sector erase operation, the device requires a maximum of 20s to suspend the erase operation. However, when the Erase Suspect command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After the erase operation has been suspected, the system can read array data from any sector not selected for erasure. (The device "erase suspends" all sectors selected for erasure.) Normal read and write timings and command definitions apply. Reading at any address within erase-suspended sectors produces status data on DQ7-DQ0. The system can use DQ7 to determine if a sector is actively erasing or is erase-suspended. See "Write Operation Status" for information on these status bits. After an erase-suspended program operation is complete, the system can once again read array data within FIGURE 2: ERASE OPERATION Erase Suspend/Erase Resume Commands The Erase Suspect command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation, including the 50s time-out period during the sector erase AS29F010 Rev. 0.3 10/02 NOTE: 1) See the appropriate Command Definitions table for program command sequence. 2) See "DQ3: Sector Erase Timer" for more information. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 8 FLASH Austin Semiconductor, Inc. non-suspended sectors. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See "Write Operation Status" for more information. The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device AS29F010 reverts to the Erase Suspend mode, and is ready for another valid operation. See "Autoselect Command Sequence" for more information. The system must write the Erase Resume command (address bits are "don't care") to exit the erase suspend mode and continue the sector erase operation. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the device has resumed erasing. TABLE 4: Command Definitions Command Sequence Read 4 5 6 1 Bus Cycles First Second Third Fourth Fifth Sixth Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data RA RD F0 AA AA AA AA AA AA AA B0 30 2AA 2AA 2AA 2AA 2AA 2AA 2AA 55 55 55 55 55 55 55 555 555 555 555 555 555 555 F0 90 90 90 A0 80 80 X00 X01 (SA) X02 PA 555 555 1 20 0 1 PD AA AA Reset Reset Cycles 2,3 1 1 XXXX Manufacturer ID Device ID Sector Protect Verify 8 Autoselect 7 3 4 4 4 4 6 6 1 1 555 555 555 555 555 555 555 XXX XXX Program Chip Erase Sector Erase Erase Suspend Erase Resume 9 10 2AA 2AA 55 55 555 SA 10 30 LEGEND: X = Don't Care RA = Address of the memory location to be read RD = Data read from location RA during read operation PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE\ or CE\ pulse, whichever happens later PD = Data to be programmed at location PA. Data latches on the rising edge of WE\ or CE\ pulse, whichever happens first SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A16-A14 uniquely select any sector. NOTES: 1. See Table 1 for description of bus operations. 2. All values are in hexadecimal. 3. Except when reading array or autoselect data, all command bus cycles are write operations. 4. No unlock or command cycles required when reading array data. 5. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high (while the device is providing status data). 6. The device accepts the three-cycle reset command sequence for backward compatibility. 7. The fourth cycle of the autoselect command sequence is a read operation. 8. The data is 00h for an unprotected sector and 01h for a protected sector. See "Autoselect Command Sequence" for more information. 9. The system may read in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation. 10. The Erase Resume command is valid only during the Erase Suspend mode. AS29F010 Rev. 0.3 10/02 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 9 FLASH Austin Semiconductor, Inc. WRITE OPERATION STATUS The device provides several bits to determine the status of a write operation: DQ3, DQ5, DQ6, and DQ7. Table 5 and the following subsections describe the functions of these bits. DQ7 and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. These three bits are discussed first. AS29F010 DQ7: Data\ Polling The Data\ Polling bit, DQ7, indicates to the host system whether an Embedded Algorithm is in progress or completed. Data\ Polling is valid after the rising edge of the final WE\ pulse in the program or erase command sequence. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data\ Polling on DQ7 is active for approximately 2s, then the device returns to reading array data. During the Embedded Erase algorithm, Data\ Polling produces a "0" on DQ7. When the Embedded Erase algorithm is complete, Data\ Polling produces a "1" on DQ7. This is analogous to the complement/true datum output described for the Embedded Program algorithm: the erase function changes all the bits in a sector to "1"; prior to this, the device outputs the "complement," or "0". The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data\ Polling on DQ7 is active for approximately 100s, then the device returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. When the system detects DQ7 has changed from the complement to true data, it can read valid data at DQ7-DQ0 on the following read cycles. This is because DQ7 may change asynchronously with DQ0-DQ6 while Output Enable (OE\) is asserted low. The Data\ Polling Timings (During Embedded Algorithms) figure in the "AC Characteristics" section illustrates this. Table 5 shows the outputs for Data\ Polling on DQ7. Figure 3 shows the Data\ Polling algorithm. Bit I may be read at any address, and is valid after the rising edge of the final WE\ pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. (The system may use either OE\ or CE\ to control the read cycles.) When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors FIGURE 3: DATA\ POLLING ALGORITHM NOTE: DQ6: Toggle Bit I Toggle bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete. Toggle AS29F010 Rev. 0.3 10/02 1) VA = Valid address for programming. During a sector erase operation, a valid address is an address within any sector selected for erasure. During chip erase, a valid address is any non-protected sector address. 2) DQ7 should be rechecked even if DQ5 = "1" because DQ7 may change simultaneously with DQ5. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 10 FLASH Austin Semiconductor, Inc. selected for erasing are protected, DQ6 toggles for approximately 100s, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. If a program address falls within a protected sector, DQ6 toggles for approximately 2s after the program command sequence is written, then returns to reading array data. The Write Operation Status table shows the outputs for Toggle Bit I on DQ6. Refer to Figure 4 for the toggle bit algorithm, and to the Toggle Bit Timings figure in the "AC Characteristics" section for the timing diagram. AS29F010 Under this condition, the device halts the operation, and when the operation has exceeded the timing limits, DQ5 produces a "1." Under both these conditions, the system must issue the reset command to return the device to reading array data. FIGURE 4: TOGGLE BIT ALGORITHM Reading Toggle Bit DQ6 Refer to Figure 4 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7-DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, a system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7-DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit it toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 4). DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a "1." This is a failure condition that indicates the program or erase cycle was not successfully completed. The DQ5 failure condition may appear if the system tries to program a "1" to a location that is previously programmed to "0." Only an erase operation can change a "0" back to a "1." AS29F010 Rev. 0.3 10/02 NOTE: 1) Read toggle bit twice to determine whether or not it is toggling. See text. 2) Recheck toggle bit because it may stop toggling as DQ5 changes to "1". See text. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 11 FLASH Austin Semiconductor, Inc. DQ3: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 to determine whether or not an erase operation has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out is complete, DQ3 switches from "0" to "1." The system may ignore DQ3 if the system can guarantee that the time between additional sector erase commands will always be less than 50s. See also the "Sector Erase Command Sequence" section. AS29F010 After the sector erase command sequence is written, the system should read the status on DQ7 (Data\ Polling) or DQ6 (Toggle Bit I) to ensure the device has accepted the command sequence, and then read DQ3. If DQ3 is "1", the internally controlled erase cycle has begun; all further commands are ignored until the erase operation is complete. If DQ3 is "0", the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 5 shows the outputs for DQ3. 1 2 TABLE 5: WRITE OPERATION STATUS OPERATION Standard Mode Erase Suspend Mode Embedded Program Algorithm Embedded Erase Algorithm Reading within Erase Suspended Sector Reading within Non-Erase Suspended Sector DQ7 DQ6 Toggle Toggle No toggle Data DQ5 0 0 0 Data DQ3 N/A 1 N/A Data DQ7\ 0 1 Data NOTES: 1. DQ7 requires a valid address when reading status information. Refer to the appropriate subsection for further details. 2. DQ5 switches to `1' when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See "DQ5: Exceeding Timing Limits" for more information. ABSOLUTE MAXIMUM RATINGS* Ambient Temperature with Power Applied............-55C to +125C Voltage with Respect to Ground VCC1.................................................................-2.0V to +7.0V A92................................................................-2.0V to +13.0V All other pins1...............................................-2.0V to +7.0V Output Short Circuit Current3..................................................200mA VCC Supply Voltage..................................................+4.50V to +5.50V Storage Temperature..................................................-65C to +125C NOTES: 1. Minimum DC voltage on input or I/O pin is -0.5V. During voltage transitions, input may overshoot VSS to -2.0V for periods of up to 20ns. See Figure 5. Maximum DC voltage on input and I/O pins is VCC + 0.5V. During voltage transitions, input and I/O pins may overshoot VCC + 2.0V for periods up to 20ns. See Figure 6. 2. Minimum DC voltage on A9 pin is -0.5V. During voltage transitions, A9 pins may overshoot VSS to -2.0V for periods of up to 20ns. See Figure 5. Maximum DC input voltage on A9 is +12.5V which may overshoot to 14.0V for periods up to 20ns. 3. No more than one output shorted at a time. Duration of the short circuit should not be greater than one second. FIGURE 5: Maximum Negative Overshoot Waveform *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. AS29F010 Rev. 0.3 10/02 FIGURE 6: Maximum Positive Overshoot Waveform Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 12 FLASH Austin Semiconductor, Inc. DC CHARACTERISTICS: TTL/NMOS Compatible PARAMETER Input Load Current A9 Input Load Current Output Leakage Current VCC Active Read Current VCC Active Write Current VCC Standby Current Input Low Voltage Input High Voltage Voltage for Autoselect and Sector Protect Output Low Voltage Output High Voltage Low VCC Lock-out Voltage VCC = 5.0V IOL = 12 mA, VCC = VCC Min IOH = -2.5 mA, VCC = VCC Min 1,2 2,3,4 AS29F010 SYM ILI ILIT ILO ICC1 ICC2 ICC3 VIL VIH VID VOL VOH VLKO 2.4 3.2 -0.5 2.0 10.5 12 30 0.4 MIN TYP MAX 5.0 100 5.0 35 50 5.0 0.8 VCC + 0.5 12.5 0.45 UNIT A A A mA mA mA V V V V V V DESCRIPTION VIN = VSS to VCC, VCC = VCC Max VCC = VCC Max, A9 = 12.5V VOUT = VSS to VCC, VCC = VCC Max CE\ = VIL, OE\ = VIH CE\ = VIL, OE\ = VIH CE\ and OE\ = VIH DC CHARACTERISTICS: CMOS Compatible PARAMETER Input Load Current A9 Input Load Current Output Leakage Current VCC Active Current VCC Active Current 1,2 2,3,4 DESCRIPTION VIN = VSS to VCC, VCC = VCC Max VCC = VCC Max, A9 = 12.5V VOUT = VSS to VCC, VCC = VCC Max CE\ = VIL, OE\ = VIH CE\ = VIL, OE\ = VIH CE\ = VCC 0.5V, OE\ = VIH SYM ILI ILIT ILO ICC1 ICC2 ICC3 VIL VIH MIN TYP MAX 5.0 50 5.0 35 50 1.6 UNIT A A A mA mA mA V V V V V VCC Standby Current Input Low Voltage Input High Voltage Voltage for Autoselect and Sector Protect Output Low Voltage Output High Voltage Low VCC Lock-out Voltage -0.5 0.7 x VCC 10.5 0.8 VCC + 0.3 12.5 0.45 VCC = 5.25V IOL = 12 mA, VCC = VCC Min IOH = -2.5 mA, VCC = VCC Min IOH = -100 A, VCC = VCC Min VID VOL VOH1 VOH2 VLKO 0.85 VCC VCC - 0.4 3.2 V NOTES: 1. 2. 3. 4. The ICC current listed is typically less than 2mA/MHz, with OE\ at VIH. Maximum ICC specifications are tested with VCC = VCC Max ICC active while Embedded Program or Embedded Erase Algorithm is in progress. Not 100% tested. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. AS29F010 Rev. 0.3 10/02 13 FLASH Austin Semiconductor, Inc. FIGURE 7: TEST CONDITIONS, Test Setup AS29F010 TABLE 6: TEST CONDITIONS, Test Specifications CONDITIONS Output Load Output Load Capacitance, CL (including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels ALL SPEEDS UNIT 1 TTL Gate 50 5 0/3 1.5 1.5 pF ns V V V AC CHARACTERISTICS: Read-Only Operations PARAMETER Read Cycle Time 1 SYMBOL JEDEC Std tAVAV tAVQV tELQV tGLQV tEHQZ 1 1 TEST SETUP MIN CE\ = VIL OE\ = VIL OE\ = VIL MAX MAX MAX MAX MAX MIN MIN MIN -50 50 50 50 25 15 15 SPEED OPTIONS -60 -70 90 -120 60 60 60 30 20 20 70 70 70 35 20 20 0 10 0 90 90 90 40 25 25 120 120 120 50 30 30 -150 UNITS 150 150 150 55 35 35 ns ns ns ns ns ns ns ns ns tRC tACC tCE tOE tDF tDF Read tOEH Toggle and Data Polling Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High Z Output Enable to Output High Z Output Enable Hold Time 1 tGHQZ Output Hold Time From Addresses CE\ or OE\, Whichever Occurs First tAXQX tOH NOTES: 1. Not 100% tested. 2. See Figure 7 and Table 6 for test specifications. AS29F010 Rev. 0.3 10/02 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 14 FLASH Austin Semiconductor, Inc. AS29F010 FIGURE 8: AC CHARACTERISTICS, Read Operations Timings AC CHARACTERISTICS: Erase and Program Operations PARAMETER Write Cycle Time 1 SYMBOL JEDEC Std MIN MIN MIN MIN MIN MIN MIN MIN MIN MIN MIN 2 -50 50 SPEED OPTIONS -60 -70 90 -120 60 70 0 90 120 -150 UNITS 150 ns ns tAVAV tAVWL tWLAX tDVWH tWHDX tWC tAS tAH tDS tDH tOES Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Read Recover Time Before Write (OE\ High to WE\ Low) CE\ Setup Time CE\ Hold Time Write Pulse Width Write Pulse Width High Byte Programming Operation Chip/Sector Erase Operation VCC Set Up Time 1 40 25 45 30 45 30 0 0 0 0 0 45 45 50 50 50 50 ns ns ns ns ns ns ns tGHWL tELWL tWHEH tWLWH tWHWL tGHWL tCS tCH tWP tWPH 25 30 35 45 20 14 60 50 50 50 ns ns s sec s MIN tWHWH1 tWHWH1 MAX tWHWH2 tWHWH2 MIN tVCS 2 NOTES: 1. Not 100% tested. 2. See the "Erase and Programming Performance" section for more information. AS29F010 Rev. 0.3 10/02 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 15 FLASH Austin Semiconductor, Inc. AS29F010 FIGURE 9: AC CHARACTERISTICS, Program Operation Timings NOTES: PA = program address, PD = program data, DOUT is the true data at the program address. FIGURE 10: AC CHARACTERISTICS, Chip/Sector Erase Operation Timings NOTES: SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see "Write Operation Status). Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. AS29F010 Rev. 0.3 10/02 16 FLASH Austin Semiconductor, Inc. AS29F010 FIGURE 11: Data\ Polling Timings (During Embedded Algorithms) NOTES: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. FIGURE 12: AC CHARACTERISTICS, Toggle Bit Timings (During Embedded Algorithms) NOTES: VA = Valid address, not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle. AS29F010 Rev. 0.3 10/02 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 17 FLASH Austin Semiconductor, Inc. AC CHARACTERISTICS: Erase and Program Operations PARAMETER Write Cycle Time 1 AS29F010 SPEED OPTIONS -60 -70 90 -120 60 70 0 90 120 SYMBOL JEDEC Std MIN MIN MIN MIN MIN tAVAV tAVEL tELAX tDVEH tEHDX tWC tAS tAH tDS tDH tOES tGHEL tWLEL tEHWH tELEH tEHEL tGHEL tWS tWH tCP tCPH -50 50 -150 UNITS 150 ns ns Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time 1 40 25 45 30 45 30 0 0 0 0 0 45 45 50 50 50 50 ns ns ns ns ns ns ns MIN MIN MIN MIN MIN MIN 2 Read Recover Time Before Write WE\ Setup Time WE\ Hold Time CE\ Pulse Width CE\ Pulse Width High Byte Programming Operation Chip/Sector Erase Operation 25 30 35 20 14 60 45 50 50 ns ns s sec MIN tWHWH1 tWHWH1 TYP tWHWH2 tWHWH2 2 NOTES: 1. Not 100% tested. 2. See the "Erase and Programming Performance" section for more information. FIGURE 13: AC CHARACTERISTICS, Alternate CE\ Controlled Write Operation Timings NOTES: 1. PA = program address, PD = program data, SA = sector address, DQ7\ = complement of data input, DOUT = array data. 2. Figure indicates the last two bus cycles of the command sequence. AS29F010 Rev. 0.3 10/02 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 18 FLASH Austin Semiconductor, Inc. ERASE AND PROGRAMMING PERFORMANCE LIMITS PARAMETER Chip/Sector Erase Time Byte Programming Time Chip Programming Time 3 AS29F010 TYP 1.0 7 0.9 1 MAX 15 300 2 UNIT sec s sec COMMENTS Excludes 00h programming prior to erasure Excludes system-level overhead 5 4 6.25 NOTES: 1. Typical program and erase times assume the following conditions: 25C, 5.0V VCC, 1 million cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90C, VCC = 4.5V, 100,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then does the device set DQ5 = 1. See the section on DQ5 for further information. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the four-but-cycle command sequence for programming. See Table 4 for further information on command definitions. 6. The device has a minimum guaranteed erase cycle endurance of 1 million cycles. LATCHUP CHARACTERISTIC PARAMETER Input voltage with respect to VSS on I/O pins VCC Current MIN -1.0V -100mA MAX VCC + 1.0V +100mA NOTES: Includes all pins except VCC. Test conditions: VCC = 5.0V, one pin at a time. PIN CAPACITANCE PARAMETER Input Capacitance Output Capacitance Control Pin Capacitance CONDITIONS VIN = 0 VOUT = 0 VPP = 0 SYMBOL CIN COUT CIN2 MAX 15 15 15 UNIT pF pF pF NOTES: 1. Sampled, not 100% tested. 2. Test conditions TA = 25C, f = 1.0 MHz DATA RETENTION PARAMETER Minimum Pattern Data Retention Time CONDITIONS 150C 125C MIN 10 20 UNIT Years Years AS29F010 Rev. 0.3 10/02 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 19 FLASH Austin Semiconductor, Inc. AS29F010 MECHANICAL DEFINITIONS* Package Designator C SYMBOL A A1 A2 B B1 D D1 D2 e e1 ASI SPECIFICATIONS MIN MAX 0.140 0.202 0.190 0.047 0.125 0.193 0.009 0.012 0.590 0.610 1.654 1.686 0.580 0.604 1.492 1.508 0.095 0.105 0.016 0.020 *All measurements are in inches. AS29F010 Rev. 0.3 10/02 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 20 FLASH Austin Semiconductor, Inc. AS29F010 ORDERING INFORMATION EXAMPLE: AS29F010CW-9/883C Speed ns Process -5** /* -6 /* -7 /* -9 /* -12 /* -15 /* Device Number Package Type AS29F010 CW AS29F010 CW AS29F010 CW AS29F010 CW AS29F010 CW AS29F010 CW *AVAILABLE PROCESSES XT = Military Temperature Range IT = Industrial Temperature Range 883C = 883C Processing Q = QML Processing -55oC to +125oC -40C to +85C -55C to +125C -55C to +125C **NOTE: 50ns (-5) option available with IT, XT, and 883C options only. AS29F010 Rev. 0.3 10/02 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 21 FLASH Austin Semiconductor, Inc. AS29F010 ASI TO DSCC PART NUMBER CROSS REFERENCE* ASI Package Designator CW ASI Part # AS29F010CW-6/Q AS29F010CW-7/Q AS29F010CW-9/Q AS29F010CW-12/Q AS29F010CW-15/Q SMD Part # 5962-9669005HYA 5962-9669004HYA 5962-9669003HYA 5962-9669002HYA 5962-9669001HYA * ASI part number is for reference only. Orders received referencing the SMD part number will be processed per the SMD. AS29F010 Rev. 0.3 10/02 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 22 |
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